# Publications and Presentations by the ACIS Lab

Explanation Capabilities in a Design-for-Testability Expert System”, International Test Conference (ITC'86). p. 954-963, 1986.

, “ A High-Level Systolic Architecture for GaAs”, 19th Hawaii International Confernce on System Sciences (HICSS). p. 253-258, 1986.

, “ A MISD Multiprocessor System for Real Time Computation of a Class of Discrete Fourier Transforms”, IEEE Transactions in Acoustics , vol. ASSP-34, no. Signal and Speech Processing, p. 1301-1310, 1986.

, “ Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays”, IEEE Transactions on Computers, vol. C-35, p. 1-13, 1986.

, “ Gracefully Degradable Processor Arrays”, IEEE Transactions on Computers, vol. C-34, p. 1033-1045, 1985.

, “ Parallelism Detection and Transformation Techniques Useful for VLSI Algorithms”, Journal of Parallel and Distributed Computing, p. 277-301, 1985.

, “ Systemic Approaches to the Design of Algorithmically Specified Systolic Arrays”, 1985 International Conference on Acoustics, Signal and Speech Processing, vol. 1. p. 300-303, 1985.

, “ On the Systolization of Polynomial Matrix Manipulations”, Midcon/85. p. 23/5.1 - 23/5.8, 1985.

, “ Data Broadcasting in Linearly Scheduled Array Processors”, 11th International Symposium on Computer Architecture. p. 224-232, 1984.

, “ Dynamically Reconfigurable Fault Tolerant Array Processors”, 14th International Symposium on Fault-Tolerant Computing. p. 386-392, 1984.

, “ Mapping an Arbitratily Large QR Algorithm into a Fixed Size VLSI Array”, 1984 International Conference on Parallel Processing. p. 364-375, 1984.

, “ A MISD Pultiprocessor System for Real Time Computation of a Class of Discrete Fourier Transforms”, 1984 Real Time Systems Symposium. p. 165-174, 1984.

, “ Optimal Linear Shcedules for the Parallel Execution of Algorithms”, 1984 International Conference on Parallel Processing. p. 322-330, 1984.

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