Publications and Presentations by the ACIS Lab

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1997
N. H. Kapadia, J. A. B. Fortes, and M. S. Lundstrom, “The Semiconductor Simulation Hub: A Network-Based Microelectronics Simulation Laboratory”, 12th Biennial IEEE University Government Industry Microelectronics Symposium. p. 72-77, 1997.
B. Z. Miled, J. A. B. Fortes, R. Eigenmann, and V. Taylor, “A Simulation-based Cost-efficiency Study of Hierarchical Heterogeneous Machines for Compiler- and Hand-Parallelized Applications”, in 9th IASTED International Conference on Parallel and Distributed Computing Systems (PDCS'97), 1997.
B. Z. Miled, J. A. B. Fortes, R. Eigenmann, and V. Taylor, “Towards the Design of a Heterogeneous Hierarchical Machine: A Simulation Approach”, 30th Simulation Conference. 1997.
1996
H. J. Lee and J. A. B. Fortes, “Automatic Generation of Modular Mappings”, International Conference on Application-Specific Systems, Architectures and Processors. p. 155-164, 1996.
M. S. Lundstrom, N. Kapadia, and J. A. B. Fortes, “The Computational Electronics Hub: A Network-Based Simulation Laboratory”, Workshop on Materials and Process Research and the Information Highway. 1996.
M. Kandaswamy, et al., “The Design of a Hierarchical Processors-and-Memory Architecture for High Performance Computing”, 6th Symposium on the Frontiers of Massively Parallel Computation (FRONTIERS '96) - Workshop on The Petaflops Frontier. 1996.
J. Miguel, A. Arruabarrena, R. Beivide, and J. A. B. Fortes, “An Empirical Evaluation of Techniques for Parallel Discrete-event Simulation of Interconnection Networks”, 4th Euro-micro Workshop on Parallel and Distributed Processing. 1996.
B. Z. Miled and J. A. B. Fortes, “A Heterogeneous Hierarchical Solution to Cost-efficient High Performance Computing”, 8th IEEE Symposium on Parallel and Distributed Processing. 1996.
B. Z. Miled, R. Eigenmann, J. A. B. Fortes, and V. Taylor, “Hierarchical Processors-and-Memory Architecture for High Performance Computing”, Sixth Symposium on the Frontiers of Massively Parallel Computation (FRONTIERS '96) - Workshop on The Petaflops Frontier. 1996.
H. V. Shah and J. A. B. Fortes, “A Library-based Approach to Symbolic Polynomial Manipulation on Distributed Memory Machines”, 8th IASTED Conference on Parallel and Distributed Computing Systems. p. 233-237, 1996.
N. Kapadia, M. S. Lundstrom, and J. A. B. Fortes, “A Network-based Simulation Hub for Microelectronic Technologies CAD”, IEEE Computer Society 1996 Annual Workshop on VLSI. 1996.
H. V. Shah and J. A. B. Fortes, “A Quasi-barrier Technique to Improve Performance of an Irregular Application”, 6th Symposium on the Frontiers of Massively Parallel Computation. p. 263-270, 1996.
1995
N. Kapadia and J. A. B. Fortes, “Block-Row Sparse Matrix-Vector Multiplication on SIMD Machines”, in 1995 International Conference on Parallel Processing, 1995, vol. III.
H. J. Lee and J. A. B. Fortes, “Communication-minimal Partitioning and Data Alignment of BLAS-like Algorithms”, in 1995 International Conference on Parallel Processing, 1995, vol. III.
H. J. Lee and J. A. B. Fortes, “Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms”, in Application Specific Array Processors, 1995. Proceedings., International Conference, 1995.
H. Cam and J. A. B. Fortes, “A Fast VLSI-efficient Self-routing Permutation Network”, IEEE Transactions on Computers, vol. 44, 1995.
H. Cam and J. A. B. Fortes, “Frames: a Simple Characterization of Permutations Realized by Frequently Used Networks”, IEEE Transactions on Computers, vol. 44, 1995.
N. Kapadia, B. Lichtenberg, J. A. B. Fortes, J. L. Gray, H. J. Siegel, and K. J. Webb, “Parallel Solution of Unstructured Sparse Finite Element Equations”, Symposium on Antennas and Propagation, vol. 2. p. 1330-1333, 1995.
H. V. Shah and J. A. B. Fortes, “Relaxation and Hybrid Approaches to Gröbner Basis Computation on Distributed Memory Machines”, in 1995 International Conference on Parallel Processing, 1995, vol. III.
H. J. Lee and J. A. B. Fortes, “Toward Data Distribution Independent Parallel Matrix Multiplication”, in Parallel Processing Symposium, 1995. Proceedings., 9th International, 1995.
H. Cam and J. A. B. Fortes, “Work-efficient Algorithms for Rearrangeable Symmetrical Networks”, 10th International Symposium on Computer and Information Sciences. p. 353-360, 1995.
1994
H. Ben-Miled, J. J. Tiemann, W. A. Helbig, and J. A. B. Fortes, “On the Design of In-phase and Quadrature Filters for Delay Compensation”, IEEE Transactions on Signal Processing, vol. 42, 1994.
J. B. Armstrong, H. J. Siegel, W. E. Cohen, T. Min, H. G. Dietz, and J. A. B. Fortes, “Dynamic task migration from SIMD to SPMD virtual machines”, in Parallel Processing, 1994. ICPP 1994. International Conference , 1994, vol. 2.
P. Boulet and J. A. B. Fortes, “Experimental evaluation of affine schedules for matrix multiplication on the MasPar architecture ”, in Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference , 1994.
H. J. Lee and J. A. B. Fortes, “On the Injectivity of Modular Mappings”, in Application Specific Array Processors, 1994. Proceedings. International Conference, 1994.

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