Publications and Presentations by the ACIS Lab

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1994
W. Shang, M. T. O'Keefe, and J. A. B. Fortes, “On loop transformations for generalized cycle shrinking”, Parallel and Distributed Systems, IEEE Transactions , vol. 5, no. 2, 1994.
J. Llosa, M. Valero, J. A. B. Fortes, and E. Ayguade, “Using Sacks to Organize Registers in VLIW Machines”, in Proceedings of the Third joint International Conference on Vector and Parallel Processing, 1994.
1993
G. Saghi, H. J. Siegel, and J. A. B. Fortes, “On the Practical Application of a Quantitative Model of System Reconfiguration Due to a Fault ”, in Parallel Processing, 1993. ICPP 1993. International Conference, 1993, vol. 3.
1992
Z. Yang, W. Shang, and J. A. B. Fortes, “Conflict-Free Scheduling of Nested Loop Algorithms on Lower Dimensional Processor Arrays”, in Parallel Processing Symposium, 1992. Proceedings., Sixth International, 1992.
D. Rau, J. A. B. Fortes, and H. J. Siegel, “Destination Tag Routing Techniques Based on a State Model for the IADM Network”, IEEE Transactions on Computers , vol. 41, no. 3, p. 274-285, 1992.
N. Lopez-Benitez and J. A. B. Fortes, “Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays”, IEEE Transactions on Computers, vol. 41, 1992.
H. Cam and J. A. B. Fortes, “Fault-Tolerant Self-Routing Permutation Networks”, in International Conference on Parallel Processing, 1992, vol. I.
W. Shang and J. A. B. Fortes, “Independent partitioning of algorithms with uniform dependencies”, Computers, IEEE Transactions on , vol.41, no.2, pp.190,206, Feb 1992, 1992.
M. T. O'Keefe and J. A. B. Fortes, “On the Relationship Between Two Systolic Array Design Methodologies”, IEEE Transactions on Computers, vol. 42, 1992.
W. Shang and J. A. B. Fortes, “On time mapping of uniform dependence algorithms into lower dimensional processor arrays”, Parallel and Distributed Systems, IEEE Transactions on , vol.3, no.3, pp.350,363, May 1992, 1992.
1991
W. Shang and J. A. B. Fortes, “Exploiting Parallelism with Linear Schedules”, in International Conference for Young Computer Scientists, Beijing, China, 1991.
W. Shang and J. A. B. Fortes, “Mapping algorithms onto parallel architectures: time schedules”, in Design and Application of Parallel Digital Processors, 1991., Second International Specialist Seminar , 1991.
W. Shang and J. A. B. Fortes, “Time optimal linear schedules for algorithms with uniform dependencies”, IEEE Transactions on Computers, vol. 40, p. 723-742, 1991.
1990
M. Chean and J. A. B. Fortes, “The Full-Use-of-Suitable-Spaces (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerance Processor Arrays”, IEEE Transactions on Computers, vol. 39, p. 564-571, 1990.
H. Cam and J. A. B. Fortes, “Rearrangeability of shuffle-exchange networks”, in Frontiers of Massively Parallel Computation, 1990. Proceedings., 3rd Symposium, 1990.
M. Chean and J. A. B. Fortes, “A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays”, IEEE Computer, p. 55-69, 1990.
1989
W. Shang and J. A. B. Fortes, “On the Optimality of Linear Schedules”, Journal of VLSI Signal Processing, vol. 1, p. 209-220, 1989.
1987
J. A. B. Fortes, “Status and Future of DEFT: A Design-for-Testability Expert Systems”, in IEEE Computer Society VLSI Workshop, 1987.
J. A. B. Fortes and B. W. Wah, “Systolic Arrays - From Concept to Implementation”, IEEE Computer, p. 12-17, 1987.
1986
J. A. B. Fortes, “Algorithm Reconfiguration Techniques for Gracefully Degradable Processor Arrays”, in International Workshop on Systolic Arrays, 1986.
M. T. O'Keefe and J. A. B. Fortes, “A Comparative Study of Two Systematic Design Methodologies for Systolic Arrays (Extended Version)”, International Workshop on Parallel Agorithms and Architectures. p. 313-324, 1986.
M. T. O'Keefe and J. A. B. Fortes, “A Comparative Study of Two Systematic Design Methodologies for Systolic Arrays”, International Conference on Parallel Processing. p. 672-675, 1986.
M. A. Samad and J. A. B. Fortes, “DEFT - A Design-for-Testability Expert Systems”, Fall Joint Computer Conference. p. 899-908, 1986.
M. T. O'Keefe and J. A. B. Fortes, “Degradable Processor Arrays”, International Conference on Parallel Processing. p. 672-675, 1986.

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