Publications and Presentations by the ACIS Lab

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J. 'A. B. Fortes, “Transnational Digital Government Research”, in 6th Annual National Conference on Digital Government Research, 2005.
J. A. B. Fortes, V. M. Milutinovic, R. Dick, W. Helbig, and W. Moyers, “A High-Level Systolic Architecture for GaAs”, 19th Hawaii International Confernce on System Sciences (HICSS). p. 253-258, 1986.
J. A. B. Fortes, “Future Challenges in VLSI System Design”, in IEEE Computer Society Annual Symposium on VLSI, 2003.
J. A. B. Fortes and C. S. Raghavendra, “Dynamically Reconfigurable Fault Tolerant Array Processors”, 14th International Symposium on Fault-Tolerant Computing. p. 386-392, 1984.
J. A. B. Fortes, “Algorithm Reconfiguration Techniques for Gracefully Degradable Processor Arrays”, in International Workshop on Systolic Arrays, 1986.
J. A. B. Fortes, R. J. Figueiredo, and M. S. Lundstrom, “Virtual Computing Infrastructures for Nanoelectronics Simulation”, Proceedings of the IEEE, vol. 93, p. 1839-1847, 2005.
J. A. B. Fortes, R. Figueiredo, L. Hermer-Vazquez, J. Principe, and J. Sanchez, “A New Architecture for Deriving Dynamic Brain-Machine Interfaces”, in International Conference on Computational Science (ICCS 2006 - DDDAS Workshop), 2006.
J. A. B. Fortes, “Status and Future of DEFT: A Design-for-Testability Expert Systems”, in IEEE Computer Society VLSI Workshop, 1987.
J. 'A. B. Fortes, “Transnational Digital Government Research”, in 5th annual National Conference on Digital Government Research, 2004.
J. A. B. Fortes and F. Parisi-Presicce, “Optimal Linear Shcedules for the Parallel Execution of Algorithms”, 1984 International Conference on Parallel Processing. p. 322-330, 1984.
J. A. B. Fortes, M. Davis, J. Harris, and R. Figueiredo, “Nanoelectronic Adaptive Systems”, in Government Microcircuit Applications and Critical Technology Conference (GOMACtech), 2003.
J. A. B. Fortes and D. I. Moldovan, “Data Broadcasting in Linearly Scheduled Array Processors”, 11th International Symposium on Computer Architecture. p. 224-232, 1984.
J. A. B. Fortes and B. W. Wah, “Systolic Arrays - From Concept to Implementation”, IEEE Computer, p. 12-17, 1987.
J. A. B. Fortes, “Probabilistic Computation”, in 2006 IEEE Conference on Nanotechnology (IEEE-NANO 2006), 2006.
J. 'A. B. Fortes, V. Ravinuthula, J. Harris, and R. J. Figueiredo, “Using Time and Redundancy for Nanocomputation”, in Government Microcircuit Application and Critical Technology Conference (GOMACTech-05), 2005.
J. A. B. Fortes, K. S. Fu, and B. Wah, “Systemic Approaches to the Design of Algorithmically Specified Systolic Arrays”, 1985 International Conference on Acoustics, Signal and Speech Processing, vol. 1. p. 300-303, 1985.
J. A. B. Fortes and M. Davis, “Space-Time Delay Architectures for Molecular Electronics”, in 2nd IEEE Conference on Nanotechnology (IEEE NANO 2002), 2002.
J. A. B. Fortes and C. S. Raghavendra, “Gracefully Degradable Processor Arrays”, IEEE Transactions on Computers, vol. C-34, p. 1033-1045, 1985.
J. A. B. Fortes and D. I. Moldovan, “Parallelism Detection and Transformation Techniques Useful for VLSI Algorithms”, Journal of Parallel and Distributed Computing, p. 277-301, 1985.
J. A. B. Fortes, et al., “On the Integration of Computer Architecture and Programming Tools into Computer Curricula”, in 1999 ASEE Conference, 1999.