Publications and Presentations by the ACIS Lab

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J. Han, E. Taylor, J. Gao, and J. A. B. Fortes, “Faults, Error Bounds and Reliability of Nanoelectronic Circuits”, in IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (IEEE-ASAP 2005), 2005.
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J. Han, E. Taylor, J. Gao, and J. A. B. Fortes, “Reliability Modeling of Majority-Logic Based Nanoelectronic Circuits”, in 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 2005.
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J. Han, J. Gao, Y. Qi, P. Jonker, and J. 'A. B. Fortes, “Toward hardware-redundant, fault-tolerant logic for nanoelectronics”, IEEE Design & Test of Computers, vol. 22, no. 4, p. 328-339, 2005.