Publications and Presentations by the ACIS Lab

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J. Han, H. Chen, E. Boykin, and J. A. B. Fortes, “Reliability Evaluation of Logic Circuits Using Probablistic Gate Models”, Microelectronics Reliability, vol. 51, no. 2, p. 468-476, 2011.
J. Han, E. Boykin, H. Chen, J. Liang, and J. A. B. Fortes, “On the Reliability of Computational Structures using Majority Logic”, IEEE Transactions on Nanotechnology, 2011.
J. Han, J. Gao, Y. Qi, P. Jonker, and J. 'A. B. Fortes, “Toward hardware-redundant, fault-tolerant logic for nanoelectronics”, IEEE Design & Test of Computers, vol. 22, no. 4, p. 328-339, 2005.