Publications and Presentations by the ACIS Lab

Found 3 results
Sort by: Author [ Title (Asc)] Type Year
Filters: Author is Jie Han  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
R
J. Han, H. Chen, E. Boykin, and J. A. B. Fortes, “Reliability Evaluation of Logic Circuits Using Probablistic Gate Models”, Microelectronics Reliability, vol. 51, no. 2, p. 468-476, 2011.
J. Han, E. Boykin, H. Chen, J. Liang, and J. A. B. Fortes, “On the Reliability of Computational Structures using Majority Logic”, IEEE Transactions on Nanotechnology, 2011.
T
J. Han, J. Gao, Y. Qi, P. Jonker, and J. 'A. B. Fortes, “Toward hardware-redundant, fault-tolerant logic for nanoelectronics”, IEEE Design & Test of Computers, vol. 22, no. 4, p. 328-339, 2005.