Publications and Presentations by the ACIS Lab

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1986
D. I. Moldovan and J. A. B. Fortes, “Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays”, IEEE Transactions on Computers, vol. C-35, p. 1-13, 1986.
1985
J. A. B. Fortes and C. S. Raghavendra, “Gracefully Degradable Processor Arrays”, IEEE Transactions on Computers, vol. C-34, p. 1033-1045, 1985.
J. A. B. Fortes and D. I. Moldovan, “Parallelism Detection and Transformation Techniques Useful for VLSI Algorithms”, Journal of Parallel and Distributed Computing, p. 277-301, 1985.
J. A. B. Fortes, K. S. Fu, and B. Wah, “Systemic Approaches to the Design of Algorithmically Specified Systolic Arrays”, 1985 International Conference on Acoustics, Signal and Speech Processing, vol. 1. p. 300-303, 1985.
S. H. Zak and J. A. B. Fortes, “On the Systolization of Polynomial Matrix Manipulations”, Midcon/85. p. 23/5.1 - 23/5.8, 1985.
1984
J. A. B. Fortes and D. I. Moldovan, “Data Broadcasting in Linearly Scheduled Array Processors”, 11th International Symposium on Computer Architecture. p. 224-232, 1984.
J. A. B. Fortes and C. S. Raghavendra, “Dynamically Reconfigurable Fault Tolerant Array Processors”, 14th International Symposium on Fault-Tolerant Computing. p. 386-392, 1984.
D. I. Moldovan, C. I. Wu, and J. A. B. Fortes, “Mapping an Arbitratily Large QR Algorithm into a Fixed Size VLSI Array”, 1984 International Conference on Parallel Processing. p. 364-375, 1984.
V. M. Milutinovic, J. A. B. Fortes, and L. H. Jamieson, “A MISD Pultiprocessor System for Real Time Computation of a Class of Discrete Fourier Transforms”, 1984 Real Time Systems Symposium. p. 165-174, 1984.
J. A. B. Fortes and F. Parisi-Presicce, “Optimal Linear Shcedules for the Parallel Execution of Algorithms”, 1984 International Conference on Parallel Processing. p. 322-330, 1984.

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