Publications and Presentations by the ACIS Lab

Found 361 results
Sort by: Author [ Title (Asc)] Type Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
T. S. Kang, M. Tsugawa, J. Fortes, and T. Hirofuchi, “Poster: Reducing the Migration Times of Multiple VMs on WANs”, High Performance Computing, Networking, Storage and Analysis (SCC), 2012 SC Companion:. p. 1530-1530, 2012.
G. Saghi, H. J. Siegel, and J. A. B. Fortes, “On the Practical Application of a Quantitative Model of System Reconfiguration Due to a Fault ”, in Parallel Processing, 1993. ICPP 1993. International Conference, 1993, vol. 3.
K. Ichikawa, et al., “PRAGMA-ENT: An International SDN testbed for cyberinfrastructure in the Pacific Rim”, Concurrency and Computation: Practice and Experience, vol. 29, no. 13, 2017.
N. H. Kapadia, J. Fortes, and C. E. Brodley, “Predictive Application-Performance Modeling in a Computational Grid Environment,”, 8th IEEE International Symposium on High Performance Distributed Computing. 1999.
J. A. B. Fortes, “Probabilistic Computation”, in 2006 IEEE Conference on Nanotechnology (IEEE-NANO 2006), 2006.
S. Su, et al., “A Prototype System for Transnational Information Sharing and Process Coordination: System Demo”, in 5th Annual National Conference on Digital Government Research, Seattle, WA, 2004, p. 287-288.
N. H. Kapadia, J. A. B. Fortes, M. S. Lundstrom, and D. Royo, “PUNCH: A Computing Portal for the Virtual University”, International Journal on Engineering Education, vol. 17, 2001.
N. H. Kapadia and J. A. B. Fortes, “PUNCH: An Architecture for Web-Enabled Wide-Area Network-Computing”, Cluster Computing: The Journal of Networks, Software Tools and Applications, vol. 2, p. 153-164, 1999.
R. J. Figueiredo, N. H. Kapadia, and J. A. B. Fortes, “The PUNCH Virtual File System: Seamless Access to Decentralized Storage Services in a Computational Grid”, in 10th IEEE International Symposium on High Performance Distributed Computing (HPDC-10), San Francisco, California, August 7–9, 2001, 2001.
N. H. Kapadia, R. J. O. Figueiredo, and J. A. B. Fortes, “Punch: web portal for running tools”, IEEE MICRO (special issue on Computer Architecture Education), vol. 20, p. 38-47, 2000.
N. H. Kapadia, J. A. B. Fortes, and M. S. Lundstrom, “The Purdue University Network-Computing Hubs: Running Unmodified Simulation Tools via the WWW”, ACM Transactions on Modeling and Computer Simulation (TOMACS), vol. 10, p. 39-57, 2000.
H. V. Shah and J. A. B. Fortes, “A Quasi-barrier Technique to Improve Performance of an Irregular Application”, 6th Symposium on the Frontiers of Massively Parallel Computation. p. 263-270, 1996.
A. Matsunaga, A. Mast, and J. A. B. Fortes, “Reaching Consensus in Crowdsourced Transcription of Biocollections Information”, in e-Science (e-Science), 2014 IEEE 10th International Conference on, Guarujá, Brazil, 2014, vol. 1, p. 57-64.
H. Cam and J. A. B. Fortes, “Rearrangeability of shuffle-exchange networks”, in Frontiers of Massively Parallel Computation, 1990. Proceedings., 3rd Symposium, 1990.
R. Subramanyan, J. Miguel-Alonso, and J. A. B. Fortes, “A Reconfigurable Monitoring System for Large-Scale Network Computing”, in 9th International Euro-Par Conference, 2003.
C. Jeffery and R. J. Figueiredo, “Reducing Fault Detection Latencies in Virtually-lockstepped Systems”, in Proceedings of the 3rd Workshop on Dependable Architectures, 2008.
T. S. Kang, M. Tsugawa, J. Fortes, and T. Hirofuchi, “Reducing the Migration Times of Multiple VMs on WANs Using a Feedback Controller”, in 2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), Cambridge, MA, USA, 2013, p. 1480-1489.
M. T. O'Keefe and J. A. B. Fortes, “On the Relationship Between Two Systolic Array Design Methodologies”, IEEE Transactions on Computers, vol. 42, 1992.
H. V. Shah and J. A. B. Fortes, “Relaxation and Hybrid Approaches to Gröbner Basis Computation on Distributed Memory Machines”, in 1995 International Conference on Parallel Processing, 1995, vol. III.
J. Han, H. Chen, E. Boykin, and J. A. B. Fortes, “Reliability Evaluation of Logic Circuits Using Probablistic Gate Models”, Microelectronics Reliability, vol. 51, no. 2, p. 468-476, 2011.
V. Ravinuthula, J. Harris, and J. A. B. Fortes, “Reliability Improvement in Time-mode Nanocomputation”, in First International Conference on Bio-Nano-Informatics (BNI) Fusion, 2005.
J. Han, E. Taylor, J. Gao, and J. A. B. Fortes, “Reliability Modeling of Majority-Logic Based Nanoelectronic Circuits”, in 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 2005.
J. Han, E. Boykin, H. Chen, J. Liang, and J. A. B. Fortes, “On the Reliability of Computational Structures using Majority Logic”, IEEE Transactions on Nanotechnology, 2011.
X. Fu, T. Li, and J. Fortes, “Reliable Express Virtual Channel based Network-on-Chip under the Impact of Technology Scaling”, in International Symposium on Quality Electronic Design (ISQED), 2013.
R. Figueiredo, P. A. Dinda, and J. 'A. B. Fortes, “Resource Virtualization Renaissance”, IEEE Comlputer, vol. 38, no. 5, p. 28-31, 2005.