Publications and Presentations by the ACIS Lab

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1984
J. A. B. Fortes and D. I. Moldovan, “Data Broadcasting in Linearly Scheduled Array Processors”, 11th International Symposium on Computer Architecture. p. 224-232, 1984.
J. A. B. Fortes and C. S. Raghavendra, “Dynamically Reconfigurable Fault Tolerant Array Processors”, 14th International Symposium on Fault-Tolerant Computing. p. 386-392, 1984.
D. I. Moldovan, C. I. Wu, and J. A. B. Fortes, “Mapping an Arbitratily Large QR Algorithm into a Fixed Size VLSI Array”, 1984 International Conference on Parallel Processing. p. 364-375, 1984.
V. M. Milutinovic, J. A. B. Fortes, and L. H. Jamieson, “A MISD Pultiprocessor System for Real Time Computation of a Class of Discrete Fourier Transforms”, 1984 Real Time Systems Symposium. p. 165-174, 1984.
J. A. B. Fortes and F. Parisi-Presicce, “Optimal Linear Shcedules for the Parallel Execution of Algorithms”, 1984 International Conference on Parallel Processing. p. 322-330, 1984.
1985
J. A. B. Fortes and C. S. Raghavendra, “Gracefully Degradable Processor Arrays”, IEEE Transactions on Computers, vol. C-34, p. 1033-1045, 1985.
J. A. B. Fortes and D. I. Moldovan, “Parallelism Detection and Transformation Techniques Useful for VLSI Algorithms”, Journal of Parallel and Distributed Computing, p. 277-301, 1985.
J. A. B. Fortes, K. S. Fu, and B. Wah, “Systemic Approaches to the Design of Algorithmically Specified Systolic Arrays”, 1985 International Conference on Acoustics, Signal and Speech Processing, vol. 1. p. 300-303, 1985.
S. H. Zak and J. A. B. Fortes, “On the Systolization of Polynomial Matrix Manipulations”, Midcon/85. p. 23/5.1 - 23/5.8, 1985.
1986
J. A. B. Fortes, “Algorithm Reconfiguration Techniques for Gracefully Degradable Processor Arrays”, in International Workshop on Systolic Arrays, 1986.
M. T. O'Keefe and J. A. B. Fortes, “A Comparative Study of Two Systematic Design Methodologies for Systolic Arrays (Extended Version)”, International Workshop on Parallel Agorithms and Architectures. p. 313-324, 1986.
M. T. O'Keefe and J. A. B. Fortes, “A Comparative Study of Two Systematic Design Methodologies for Systolic Arrays”, International Conference on Parallel Processing. p. 672-675, 1986.
M. A. Samad and J. A. B. Fortes, “DEFT - A Design-for-Testability Expert Systems”, Fall Joint Computer Conference. p. 899-908, 1986.
M. T. O'Keefe and J. A. B. Fortes, “Degradable Processor Arrays”, International Conference on Parallel Processing. p. 672-675, 1986.
M. A. Samad and J. A. B. Fortes, “Explanation Capabilities in a Design-for-Testability Expert System”, International Test Conference (ITC'86). p. 954-963, 1986.
J. A. B. Fortes, V. M. Milutinovic, R. Dick, W. Helbig, and W. Moyers, “A High-Level Systolic Architecture for GaAs”, 19th Hawaii International Confernce on System Sciences (HICSS). p. 253-258, 1986.
V. M. Milutinovic, J. A. B. Fortes, and L. H. Jamieson, “A MISD Multiprocessor System for Real Time Computation of a Class of Discrete Fourier Transforms”, IEEE Transactions in Acoustics , vol. ASSP-34, no. Signal and Speech Processing, p. 1301-1310, 1986.
D. I. Moldovan and J. A. B. Fortes, “Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays”, IEEE Transactions on Computers, vol. C-35, p. 1-13, 1986.
1987
J. A. B. Fortes, “Status and Future of DEFT: A Design-for-Testability Expert Systems”, in IEEE Computer Society VLSI Workshop, 1987.
J. A. B. Fortes and B. W. Wah, “Systolic Arrays - From Concept to Implementation”, IEEE Computer, p. 12-17, 1987.
1989
W. Shang and J. A. B. Fortes, “On the Optimality of Linear Schedules”, Journal of VLSI Signal Processing, vol. 1, p. 209-220, 1989.
1990
M. Chean and J. A. B. Fortes, “The Full-Use-of-Suitable-Spaces (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerance Processor Arrays”, IEEE Transactions on Computers, vol. 39, p. 564-571, 1990.
H. Cam and J. A. B. Fortes, “Rearrangeability of shuffle-exchange networks”, in Frontiers of Massively Parallel Computation, 1990. Proceedings., 3rd Symposium, 1990.
M. Chean and J. A. B. Fortes, “A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays”, IEEE Computer, p. 55-69, 1990.

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