Toward hardware-redundant, fault-tolerant logic for nanoelectronics

TitleToward hardware-redundant, fault-tolerant logic for nanoelectronics
Publication TypeJournal Article
Year of Publication2005
AuthorsHan, J, Gao, J, Qi, Y, Jonker, P, Fortes, J'AB
JournalIEEE Design & Test of Computers
Volume22
Issue4
Pagination328-339
Date Published07/2005
AbstractThis article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage multiplexing systems. Second, we show how to obtain the fundamental error bounds by using bifurcation analysis based on probabilistic models of unreliable gates. Third, we describe the notion of random interwoven redundancy. Finally, we compare the reliabilities of quadded and random interwoven structures by using a simulation-based approach. We observe that the deeper a circuit's logical depth, the more fault-tolerant the circuit tends to be for a fixed number of faults. For a constant gate failure rate, a circuit's reliability tends to reach a stationary state as its logical depth increases.