Using Sacks to Organize Registers in VLIW Machines

TitleUsing Sacks to Organize Registers in VLIW Machines
Publication TypeConference Paper
Year of Publication1994
AuthorsLlosa, J, Valero, M, Fortes, JAB, Ayguade, E
Conference NameProceedings of the Third joint International Conference on Vector and Parallel Processing
AbstractThis paper analyses the register requirements of software pipelined inner loops. When the number of functional units and/or the number of stages of individual functional units is increased, the number of registers required may be prohibitive in chip area and cycle time. We characterize lifetime of values in pipelined loops with their loop register locality (LRL). Based on this characteristic, we propose a new organization of the register file in order not to affect cycle time and also reduce area, while increasing the number of registers. This can be useful to minimize the frequency of spill at a reasonable cost. The spill code can increase the minimum initiation interval and decrease loop performance. This new organization consists of a small high bandwidth multiported register file and a low bandwidth port-limited register file called sack. A mechanism to assign values to the sack is presented. We demonstrate the effectiveness of our approach by experimenting with a collection of ...