Publications and Presentations by the ACIS Lab

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1998
J. Miguel, A. Arruabarrena, R. Beivide, and J. A. B. Fortes, “An Evaluation of Implementations of the CMB Parallel Simulation Algorithm on Distributed Memory Multicomputers”, Journal of Systems Architecture, vol. 44, no. 6-7, p. 519–545, 1998.
N. Khanna, J. A. B. Fortes, and S. Y. Nof, “A Formalism to Structure and Parallelize the Integration of Cooperative Engineering Design Tasks”, IIE Transactions, vol. 30, no. 1, p. 1-15, 1998.
R. J. Figueiredo and J. A. B. Fortes, “Impact of Computing-in-Memory on the Performance of Processor-And-Memory Hierarchies”, in 11th International Conference on Parallel and Distributed Computing Systems (PDCS-98), 1998.
N. Kapadia, J. P. Robertson, and J. A. B. Fortes, “Interface Issues in Running Computer Architecture Tools via the World-Wide Web”, in Workshop on Computer Architecture Education (WCAE-98), 1998.
J. P. Bradford and J. A. B. Fortes, “Performance and Memory-Access Characterization of Data Mining Applications,”, in 31st Annual Symposium on Micro-architecture - Workshop on Workload Characterization, 1998.
N. Kapadia, C. Brodley, J. A. B. Fortes, and M. Lundstrom, “Resource-Usage Prediction for Demand-Based Network-Computing”, in Workshop on Advances in Parallel and Distributed Systems (APADS), 1998.
R. J. Figueiredo, J. A. B. Fortes, and B. Z. Miled, “Spatial Data Locality with Respect to Degree of Parallelism in Processor-And-Memory Hierarchies,”, in 3rd International Meeting on Vector and Parallel Processing (VECPAR98), 1998.
1997
H. J. Lee and J. A. B. Fortes, “Automatic Generation of Injective Modular Mappings”, in International Conference on Parallel Processing, 1997.
H. - J. Lee and J. A. B. Fortes, “Communication-minimal Partitioning and Data Alignment for Affine Nested Loops”, The Computer Journal, vol. 40, p. 302-310, 1997.
H. V. Shah and J. A. B. Fortes, “Effects of Dynamic Task Distributions on the Performance of a Class of Irregular Computations”, in 1997 International Conference on Parallel Processing, 1997.
H. V. Shah and J. A. B. Fortes, “Efficient Techniques for Performing an Irregular Computation on Distributed Memory Machines”, International Journal of Systems Science, vol. 28, no. 11, p. 1101-1113, 1997.
H. J. Lee, J. Robertson, and J. A. B. Fortes, “Generalized Cannon's Algorithm for Parallel Matrix Multiplication”, 11th ACM International Conference on Supercomputing. p. 44-51, 1997.
M. Kandaswamy, V. Taylor, R. Eigenmann, and J. A. B. Fortes, “Implicit Finite Element Applications: A Case for Matching the Number of Processors to the Dynamics of the Program Execution”, 8th SIAM Conference on Parallel Processing. 1997.
H. - J. Lee and J. A. B. Fortes, “Modular Mappings and Data Distribution Independent Computations”, Parallel Processing Letters, vol. 7, no. 2, p. 169-180, 1997.
N. H. Kapadia, M. S. Lundstrom, J. A. B. Fortes, and K. Rooy, “Network-Based Simulation Laboratories for Microelectronics Systems Design and Education”, International Conference on Microelectronic Systems Education. p. 23-24, 1997.
N. H. Kapadia, J. A. B. Fortes, and M. S. Lundstrom, “The Semiconductor Simulation Hub: A Network-Based Microelectronics Simulation Laboratory”, 12th Biennial IEEE University Government Industry Microelectronics Symposium. p. 72-77, 1997.
B. Z. Miled, J. A. B. Fortes, R. Eigenmann, and V. Taylor, “A Simulation-based Cost-efficiency Study of Hierarchical Heterogeneous Machines for Compiler- and Hand-Parallelized Applications”, in 9th IASTED International Conference on Parallel and Distributed Computing Systems (PDCS'97), 1997.
B. Z. Miled, J. A. B. Fortes, R. Eigenmann, and V. Taylor, “Towards the Design of a Heterogeneous Hierarchical Machine: A Simulation Approach”, 30th Simulation Conference. 1997.
1996
H. J. Lee and J. A. B. Fortes, “Automatic Generation of Modular Mappings”, International Conference on Application-Specific Systems, Architectures and Processors. p. 155-164, 1996.
M. S. Lundstrom, N. Kapadia, and J. A. B. Fortes, “The Computational Electronics Hub: A Network-Based Simulation Laboratory”, Workshop on Materials and Process Research and the Information Highway. 1996.
M. Kandaswamy, et al., “The Design of a Hierarchical Processors-and-Memory Architecture for High Performance Computing”, 6th Symposium on the Frontiers of Massively Parallel Computation (FRONTIERS '96) - Workshop on The Petaflops Frontier. 1996.
J. Miguel, A. Arruabarrena, R. Beivide, and J. A. B. Fortes, “An Empirical Evaluation of Techniques for Parallel Discrete-event Simulation of Interconnection Networks”, 4th Euro-micro Workshop on Parallel and Distributed Processing. 1996.
B. Z. Miled and J. A. B. Fortes, “A Heterogeneous Hierarchical Solution to Cost-efficient High Performance Computing”, 8th IEEE Symposium on Parallel and Distributed Processing. 1996.
B. Z. Miled, R. Eigenmann, J. A. B. Fortes, and V. Taylor, “Hierarchical Processors-and-Memory Architecture for High Performance Computing”, Sixth Symposium on the Frontiers of Massively Parallel Computation (FRONTIERS '96) - Workshop on The Petaflops Frontier. 1996.
H. V. Shah and J. A. B. Fortes, “A Library-based Approach to Symbolic Polynomial Manipulation on Distributed Memory Machines”, 8th IASTED Conference on Parallel and Distributed Computing Systems. p. 233-237, 1996.

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