# Publications and Presentations by the ACIS Lab

Spatial Data Locality with Respect to Degree of Parallelism in Processor-And-Memory Hierarchies,”, in 3rd International Meeting on Vector and Parallel Processing (VECPAR98), 1998.

, “ Automatic Generation of Injective Modular Mappings”, in International Conference on Parallel Processing, 1997.

, “ Communication-minimal Partitioning and Data Alignment for Affine Nested Loops”, The Computer Journal, vol. 40, p. 302-310, 1997.

, “ Effects of Dynamic Task Distributions on the Performance of a Class of Irregular Computations”, in 1997 International Conference on Parallel Processing, 1997.

, “ Efficient Techniques for Performing an Irregular Computation on Distributed Memory Machines”, International Journal of Systems Science, vol. 28, no. 11, p. 1101-1113, 1997.

, “ Generalized Cannon's Algorithm for Parallel Matrix Multiplication”, 11th ACM International Conference on Supercomputing. p. 44-51, 1997.

, “ Implicit Finite Element Applications: A Case for Matching the Number of Processors to the Dynamics of the Program Execution”, 8th SIAM Conference on Parallel Processing. 1997.

, “ Modular Mappings and Data Distribution Independent Computations”, Parallel Processing Letters, vol. 7, no. 2, p. 169-180, 1997.

, “ Network-Based Simulation Laboratories for Microelectronics Systems Design and Education”, International Conference on Microelectronic Systems Education. p. 23-24, 1997.

, “ The Semiconductor Simulation Hub: A Network-Based Microelectronics Simulation Laboratory”, 12th Biennial IEEE University Government Industry Microelectronics Symposium. p. 72-77, 1997.

, “ A Simulation-based Cost-efficiency Study of Hierarchical Heterogeneous Machines for Compiler- and Hand-Parallelized Applications”, in 9th IASTED International Conference on Parallel and Distributed Computing Systems (PDCS'97), 1997.

, “ Towards the Design of a Heterogeneous Hierarchical Machine: A Simulation Approach”, 30th Simulation Conference. 1997.

, “ Automatic Generation of Modular Mappings”, International Conference on Application-Specific Systems, Architectures and Processors. p. 155-164, 1996.

, “ The Computational Electronics Hub: A Network-Based Simulation Laboratory”, Workshop on Materials and Process Research and the Information Highway. 1996.

, “ The Design of a Hierarchical Processors-and-Memory Architecture for High Performance Computing”, 6th Symposium on the Frontiers of Massively Parallel Computation (FRONTIERS '96) - Workshop on The Petaflops Frontier. 1996.

, “ An Empirical Evaluation of Techniques for Parallel Discrete-event Simulation of Interconnection Networks”, 4th Euro-micro Workshop on Parallel and Distributed Processing. 1996.

, “ A Heterogeneous Hierarchical Solution to Cost-efficient High Performance Computing”, 8th IEEE Symposium on Parallel and Distributed Processing. 1996.

, “ Hierarchical Processors-and-Memory Architecture for High Performance Computing”, Sixth Symposium on the Frontiers of Massively Parallel Computation (FRONTIERS '96) - Workshop on The Petaflops Frontier. 1996.

, “ A Library-based Approach to Symbolic Polynomial Manipulation on Distributed Memory Machines”, 8th IASTED Conference on Parallel and Distributed Computing Systems. p. 233-237, 1996.

, “ A Network-based Simulation Hub for Microelectronic Technologies CAD”, IEEE Computer Society 1996 Annual Workshop on VLSI. 1996.

, “ A Quasi-barrier Technique to Improve Performance of an Irregular Application”, 6th Symposium on the Frontiers of Massively Parallel Computation. p. 263-270, 1996.

, “ Block-Row Sparse Matrix-Vector Multiplication on SIMD Machines”, in 1995 International Conference on Parallel Processing, 1995, vol. III.

, “ Communication-minimal Partitioning and Data Alignment of BLAS-like Algorithms”, in 1995 International Conference on Parallel Processing, 1995, vol. III.

, “ Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms”, in Application Specific Array Processors, 1995. Proceedings., International Conference, 1995.

, “ A Fast VLSI-efficient Self-routing Permutation Network”, IEEE Transactions on Computers, vol. 44, 1995.

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