Publications and Presentations by the ACIS Lab

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G
A. Ganguly, A. Agrawal, P. O. Boykin, and R. J. Figueiredo, “WOW: Self-organizing Wide-area Overlay Networks of Virtual Workstations”, in Proc. High Performance Distributed Computing (HPDC), 2006.
A. Ganguly, A. Agrawal, P. O. Boykin, and R. J. Figueiredo, “WOW: Self-organizing Wide-area Overlay Networks of Virtual Workstations”, Journal of Grid Computing, vol. 5, no. 2, p. 151-172, 2007.
A. Ganguly, P. O. Boykin, and R. J. Figueiredo, “Techniques for Low-latency Proxy Selection in Wide-area P2P Networks”, in Proceedings of Seventh International Workshop on Hot Topics in Peer-to-Peer Systems (HotP2P), 2010.
A. Ganguly, A. Agrawal, P. O. Boykin, and R. J. Figueiredo, “IP over P2P: Enabling Self-configuring Virtual IP Networks for Grid Computing”, in Proc. 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2006.
A. Ganguly, D. Wolinsky, P. O. Boykin, and R. J. Figueiredo, “Decentralized Dynamic Host Configuration in Wide-Area Overlay Networks of Virtual Workstations”, in Workshop on Large-Scale and Volatile Desktop Grids (PCGrid @ IPDPS), 2007.
A. Ganguly, D. Wolinsky, P. O. Boykin, and R. J. Figueiredo, “Improving Peer Connectivity in Wide-area Overlays of Virtual Workstations”, Cluster Computing, vol. 12, no. 2, p. 239-256, 2009.
A. Ganguly, D. Wolinsky, P. O. Boykin, and R. J. Figueiredo, “Improving Peer Connectivity in Wide-area Overlays of Virtual Workstations”, in Proceedings of the Symposium on High-Performance Distributed Computing (HPDC), 2008.
J. B. Gao, Y. Qi, and J. 'A. B. Fortes, “Bifurcations and fundamental error bounds for fault-tolerant computations”, IEEE Transactions on Nanotechnology, vol. 4, no. 4, p. 395-402, 2005.
H
J. Han, J. Gao, Y. Qi, P. Jonker, and J. 'A. B. Fortes, “Toward hardware-redundant, fault-tolerant logic for nanoelectronics”, IEEE Design & Test of Computers, vol. 22, no. 4, p. 328-339, 2005.
J. Han, E. Boykin, H. Chen, J. Liang, and J. A. B. Fortes, “On the Reliability of Computational Structures using Majority Logic”, IEEE Transactions on Nanotechnology, 2011.
J. Han, H. Chen, E. Boykin, and J. A. B. Fortes, “Reliability Evaluation of Logic Circuits Using Probablistic Gate Models”, Microelectronics Reliability, vol. 51, no. 2, p. 468-476, 2011.
J. Han, E. Taylor, J. Gao, and J. A. B. Fortes, “Faults, Error Bounds and Reliability of Nanoelectronic Circuits”, in IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (IEEE-ASAP 2005), 2005.
J. Han, E. Taylor, J. Gao, and J. A. B. Fortes, “Reliability Modeling of Majority-Logic Based Nanoelectronic Circuits”, in 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 2005.
W. Hassanein, J. A. B. Fortes, and R. Eigenmann, “Towards Guided Data Forwarding Using Intelligent Memory”, in 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), 2002.
W. Hassanein, J. 'A. B. Fortes, and R. Eigenmann, “Data Forwarding through In- Memory Precomputation Threads”, in International Conference on Supercomputing (ICS), 2004.
T. Hirofuchi, M. Tsugawa, H. Nakada, T. Kudoh, and S. Itoh, “A WAN-Optimized Live Storage Migration Mechanism toward Virtual Machine Evacuation upon Severe Disasters”, IEICE TRANSACTIONS on Information and Systems, vol. E96-D, no. 12, p. 2663-2674, 2013.
T. Hirofuchi, M. Tsugawa, H. Nakada, S. Itoh, and S. Sekiguchi, “仮想マシンの超広域ライブマイグレーションにむけたベストエフォート型状態同期機構の試作 ”, vol. 2012-OS-121, no. 11. 2012.
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K. Ichikawa, et al., “PRAGMA-ENT: An International SDN testbed for cyberinfrastructure in the Pacific Rim”, Concurrency and Computation: Practice and Experience, vol. 29, no. 13, 2017.
J
S. A. James, et al., “Herbarium data: Global biodiversity and societal botanical needs for novel research”, Applications in Plant Sciences, vol. 6, p. e1024–n/a, 2018.
C. Jeffery and R. J. Figueiredo, “Hierarchical Fault-tolerance for Nanoscale Memories”, IEEE Transactions of Nanotechnology, vol. 5, no. 4, p. 407-414, 2006.
C. Jeffery and R. J. Figueiredo, “A Flexible Approach to Improving System Reliability with Virtual Lockstep”, IEEE Transactions on Dependable and Secure Computing, vol. 9, no. 1, p. 2-15, 2012.
C. Jeffery, A. Basagalar, and R. J. Figueiredo, “Dynamic Sparing and Error Correction Techniques for Fault Tolerance in Nanoscale Memory Structures”, Proc. IEEE International Conference on Nanotechnology (NANO). 2004.
C. Jeffery and R. J. Figueiredo, “Reducing Fault Detection Latencies in Virtually-lockstepped Systems”, in Proceedings of the 3rd Workshop on Dependable Architectures, 2008.
C. Jeffery and R. J. Figueiredo, “Towards Byzantine Fault Tolerance in Many-core Computing Platforms”, in IEEE Pacific Rim Dependable Computing Conference (PRDC), 2007.

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