Publications and Presentations by the ACIS Lab

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J. Han, E. Taylor, J. Gao, and J. A. B. Fortes, “Faults, Error Bounds and Reliability of Nanoelectronic Circuits”, in IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (IEEE-ASAP 2005), 2005.
J. Han, J. Gao, Y. Qi, P. Jonker, and J. 'A. B. Fortes, “Toward hardware-redundant, fault-tolerant logic for nanoelectronics”, IEEE Design & Test of Computers, vol. 22, no. 4, p. 328-339, 2005.
J. Han, E. Boykin, H. Chen, J. Liang, and J. A. B. Fortes, “On the Reliability of Computational Structures using Majority Logic”, IEEE Transactions on Nanotechnology, 2011.
J. Han, H. Chen, E. Boykin, and J. A. B. Fortes, “Reliability Evaluation of Logic Circuits Using Probablistic Gate Models”, Microelectronics Reliability, vol. 51, no. 2, p. 468-476, 2011.
J. Han, E. Taylor, J. Gao, and J. A. B. Fortes, “Reliability Modeling of Majority-Logic Based Nanoelectronic Circuits”, in 5th IEEE Conference on Nanotechnology (IEEE-NANO 2005), 2005.
W. Hassanein, J. A. B. Fortes, and R. Eigenmann, “Towards Guided Data Forwarding Using Intelligent Memory”, in 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), 2002.
W. Hassanein, J. 'A. B. Fortes, and R. Eigenmann, “Data Forwarding through In- Memory Precomputation Threads”, in International Conference on Supercomputing (ICS), 2004.
T. Hirofuchi, M. Tsugawa, H. Nakada, S. Itoh, and S. Sekiguchi, “仮想マシンの超広域ライブマイグレーションにむけたベストエフォート型状態同期機構の試作 ”, vol. 2012-OS-121, no. 11. 2012.
T. Hirofuchi, M. Tsugawa, H. Nakada, T. Kudoh, and S. Itoh, “A WAN-Optimized Live Storage Migration Mechanism toward Virtual Machine Evacuation upon Severe Disasters”, IEICE TRANSACTIONS on Information and Systems, vol. E96-D, no. 12, p. 2663-2674, 2013.